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LX5261
TM (R)
27-Line LVD SCSI Source/Sink Regulator
PRODUCTION DATASHEET
DESCRIPTION
KEY FEATURES
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The LX5261 is a source/sink regulator designed to provide the correct reference voltages and bias currents for SCSI LVD applications. With the proper LVD termination network (475, 121, 475), the LX5261 assures that LVD performance is compliant to the SPI-2 (Ultra2), SPI3 (Ultra160) and SPI-4 (Ultra320) specification. The LX5261 provides two fixed regulated outputs (1.75V and 0.75V)
each capable of sourcing / sinking 200mA, along with a buffered 1.3V output for DIFSENS signaling. The LX5261 features on-chip trimming of the internal voltage enabling precise output voltages; typically +/- 1% of its specified value. Thermal Shutdown and Current Limiting is integrated onchip. The LX5261 is available in the 16pin SOIC (DP) package.
Compliant with SPI-2 (Ultra2), SPI-3 (Ultra160), and SPI-4 (Ultra320) 2.7V to 5.25V Operation 200mA Source/Sink Capability DIFSENS Line Driver Current Limit and Thermal Protection Pin Compatible With Unitrode UCC561
IMPORTANT: For the most current data, consult MICROSEMI's website: http://www.microsemi.com
TYPICAL APPLICATION
1.3V Reference 2 4.7uF 1.75V Reference
VTERM 2.7V to 5.25V
+ -
1.3V +/- 0.1V
7
DIFSENS
+ -
1.75V +/- 0.05V 200mA source/sink 6
VOUT1
475 1% L1121 1% 475 1%
4.7uF 0.75V Reference 4 0.75V +/- 0.05V 200mA source/sink 3 VOUT2
GND
+ -
L1+ 27 LVD Pairs L27121 1% L27+
4.7uF 475 1%
475 1%
LX5261 LX5261
PACKAGE ORDER INFO SOIC DP 16-Pin TA (C) 0 to 70
RoHS Compliant / Pb-free Transition DC: 0440
LX5261CDP
Note: Available in Tape & Reel. Append the letters "TR" to the part number. (i.e. LX5261CDP-TR)
Copyright (c) 2000 Rev. 1.0c, 2005-02-08
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
LX5261
TM (R)
27-Line LVD SCSI Source/Sink Regulator
PRODUCTION DATASHEET
ABSOLUTE MAXIMUM RATINGS Term Power (VTERM) .........................................................................................................6V Operating Junction Temperature..................................................................................... 150C Storage Temperature Range..............................................................................-65C to 150C RoHS / Pb-freePeak Package Solder Reflow Temperature (40 second maximum exposure) ........................................................................ 260C (+0, -5)
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal.
PACKAGE PIN OUT
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N/C VTERM VOUT2 GND HSGND VOUT1 DIFSENS
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
N/C N/C N/C HSGND HSGND N/C N/C N/C
THERMAL DATA
N/C
DP PACKAGE
DP
16-Pin SOIC 111.8 C/W
(Top View) NC - No Internal Connection
THERMAL RESISTANCE-JUNCTION TO AMBIENT, JA
RoHS / Pb-free 100% Matte Tin Lead Finish
Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. JA can vary significantly depending on mounting technique. (See Application Notes Section: Thermal considerations) FUNCTIONAL PIN DESCRIPTION PIN NAME VOUT1 VOUT2 DESCRIPTION 1.75V Regulated Output. Capable of sourcing/sinking 200mA. 0.75V Regulated Output. Capable of sourcing/sinking 200mA.
Power supply pin for terminator. Connect to SCSI bus VTERM. Usually decoupled by one 4.7F low-ESR capacitor. It is absolutely necessary to connect this pin to the
VTERM decoupling capacitor through a very low impedance (big traces to PCB). Keeping distances very short from the decoupling capacitors is somewhat layout dependent and some applications may benefit from high frequency decoupling with 0.1F capacitors at VTERM pin. 1.3V buffered output for DIFSENS signaling.
DIFSENS GND HSGND
PACKAGE DATA PACKAGE DATA
Regulator ground pin. Connect to ground. Attached to die mounting pad, but not bonded to GND pin. Pins should be considered a heat sink only, and not a true ground connection. It is recommended that these pins be connected to ground, but can be left floating.
Copyright (c) 2000 Rev. 1.0c, 2005-02-08
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
LX5261
TM (R)
27-Line LVD SCSI Source/Sink Regulator
PRODUCTION DATASHEET
RECOMMENDED MAX OPERATING CONDITIONS Parameter
VTERM Signal Line Voltage Operating Junction Temperature TJ
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Symbol
VTERM
Min
2.7 0 0
LX5261 Typ
Max
5.25 5.0 70
Units
V V C
ELECTRICAL CHARACTERISTICS Unless otherwise specified, the following specifications apply over the operating ambient temperature 0C TA 70C, and VTERM = 3.3V. Parameter
TERMPWR Section VTERM Supply Current VTERM Voltage Regulator Section 1.75V Regulator 1.3V Regulator 0.75V Regulator 1.75V Regulator Source Current 1.75V Regulator Sink Current 1.75V Source Current Limit 1.75V Sink Current Limit 1.3V Regulator Source Current 1.3V Regulator Sink Current 0.75V Regulator Source Current 0.75V Regulator Sink Current 0.75V Source Current Limit 0.75V Sink Current Limit IDIFS_SRC IDIFS_SNK ISRC2 ISNK2 DIFSENS; 0V DIFSENS = 2.4V VOUT = 0.25V VOUT = 1.25V 200 -700 700 -5 50 VREG1 VDIFS VREG2 ISRC1 ISNK1 -125mA < IOUT < 125mA, 2.7V < VIN < 5.25V DIFSENS; No Load -125mA < IOUT < 125mA, 2.7V < VIN < 5.25V VOUT = 1.25V VOUT = 2.25V 200 -700 700 -15 200 -200 1.7 1.2 0.7 1.75 1.3 0.75 1.8 1.4 0.8 -200 V V V mA mA mA mA mA A mA mA mA mA ITERM VTERM No Load 2.7 35 40 5.25 mA V
Symbol
Test Conditions
Min
LX5261 Typ
Max
Units
ELECTRICALS ELECTRICALS
Copyright (c) 2000 Rev. 1.0c, 2005-02-08
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
LX5261
TM (R)
27-Line LVD SCSI Source/Sink Regulator
PRODUCTION DATASHEET
BLOCK DIAGRAM
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1.3V Reference VTERM 2
+ -
1.3V +/- 0.1V 7 DIFSENS
1.75V Reference
+ -
1.75V +/- 0.05V 200mA source/sink 6 VOUT1
GND 4 0.75V +/- 0.05V 200mA source/sink 3 VOUT2
0.75V Reference
+ -
Figure 1 - LX5261 Block Diagram APPLICATION INFORMATION LVD SCSI with Resistor Stack The LX5261 is used with a LVD resistor network (475, 121, 475) to meet LVD SCSI performance. Connecting the top side of the LVD resistor network to the 1.75V regulated output (VREG1, pin 6), and the bottom side of the LVD resistor network to the 0.75 regulated output (VREG2, pin 3) provides the correct bias voltage, differential impedance, common mode differential impedance, and common mode voltage required by the SPI-2 through SPI-4 SCSI specification (see Figure 2. below). The LX5261 is designed to drive up to 27 LVD pairs.
1.75V +/- 0.05V 200mA source/sink 6 475 1%
+ -
VOUT1
27
Ln-
Parameter
121 1 of 27 1% LVD Pairs 27 475 1% Ln+
LX5261 107.3 112.9 237 1.25
SCSI Standard 100 to 110 100 to 125 100 to 300 1.2 to 1.3
Units ohm mV ohm V
4.7uF 0.75V +/- 0.05V 200mA source/sink 3 VOUT2
Differential Impedance Differential Bias Voltage Common Mode Impedance Common Mode Voltage
BLOCK DIAGRAM BLOCK DIAGRAM
+ -
4.7uF
Figure 2 - LX5261 with LVD Resistor Stack
Copyright (c) 2000 Rev. 1.0c, 2005-02-08
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
LX5261
TM (R)
27-Line LVD SCSI Source/Sink Regulator
PRODUCTION DATASHEET
MECHANICAL DRAWINGS
WWW .Microsemi .C OM
DP
16-Pin Small Outline Package (SOIC) Narrow Body
F
B
P
1
2 D
3
G A L C K M J
Dim A B C D F G J K L M P *LC
Note:
MILLIMETERS MIN MAX 9.78 10.01 3.81 4.01 1.35 1.75 0.35 0.46 0.77 1.27 BSC 0.19 0.25 0.10 0.25 4.82 5.21 0 8 5.79 6.20 0.10
INCHES MIN MAX 0.385 0.394 0.150 0.158 0.053 0.069 0.014 0.018 0.030 0.050 BSC 0.007 0.010 0.004 0.010 0.189 0.205 0 8 0.228 0.244 0.004
MECHANICALS MECHANICALS
1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm (.006") on any side. Lead dimension shall not include solder coverage.
Copyright (c) 2000 Rev. 1.0c, 2005-02-08
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
LX5261
TM (R)
27-Line LVD SCSI Source/Sink Regulator
PRODUCTION DATASHEET
NOTES
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NOTES NOTES
PRODUCTION DATA - Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time.
Copyright (c) 2000 Rev. 1.0c, 2005-02-08
Microsemi
Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6

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